Divyanshu Saxena
I am a postdoctoral scholar in the NetSys Lab at University of California, Berkeley, where I am hosted by Prof. Rishabh Iyer. I am broadly interested in Systems and Networking, with a focus on building robust, adaptive, and performant systems using agentic and learning-based techniques.
Previously, I was a graduate student at University of Texas at Austin, where I was advised by Prof. Aditya Akella as a part of the UT Networked Systems Lab and the LDOS Project. My Ph.D. thesis was on designing abstractions and interfaces for computer systems so that operators can realize complex performance requirements under dynamic contexts.
Even before that, I was an undergraduate student at the Indian Institute of Technology, Delhi majoring in Computer Science and Engineering where I met and made friends with some absolutely amazing and competent people. I hail from Lucknow, a city in Northern India.
News
| Aug 20, 2026 | Our paper on using LLMs to synthesize specialized, verifiable heuristics is conditionally accepted to appear at EuroSys â27! |
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| Jul 11, 2026 | Our paper on counterfactual performance reasoning for DRAM sizing, TierSizer, accepted to appear at DIMES workshop at SOSPâ26! |
| Jun 25, 2026 |
Successfully defended my PhD thesis at UT Austin! |
| May 22, 2026 |
MatchBox received a Distinguished Paper Award at PLDIâ26! |
| Apr 3, 2026 | Our paper MatchBox on a semantic foundation for data plane portability is accepted to appear at PLDIâ26! |
| Dec 10, 2025 | Our paper on designing robust learning-based microservice controllers is accepted to appear at NSDIâ26! |
| Nov 30, 2025 | Work done at Microsoft during Summer 2025 is set to appear at the LLM4Code workshop at ICSEâ26! |
| Sep 16, 2025 | Our framework for using LLMs to generate instance-optimal policies, PolicySmith, accepted to appear at HotNetsâ25! |
| Aug 23, 2025 | Our paper on integrating verification in the learning of congestion controllers is accepted to appear at EuroSysâ26! |